ISL12057IUZ【PDF 5/17 页】IC RTC/CALENDAR I2C 8-MSOP

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FN6755.1

March 3, 2011

Device Addressing

Following a start condition, the master must output a Slave

Address Byte. The seven MSBs are the device identifier.

These bits are “1101000”. Slave bits “1101” access the

The last bit of the Slave Address Byte defines a read or write

operation to be performed. When this R/W bit is a “1”, then a

read operation is selected. A “0” selects a write operation

(see Figure 10).

After loading the entire Slave Address Byte from the SDA

bus, the ISL12057 compares the device identifier and device

select bits with “1101000”. Upon a correct compare, the

device outputs an acknowledge on the SDA line.

Following the Slave Byte is a one-byte word address. The

word address is either supplied by the master device or

obtained from an internal counter. On power-up, the internal

address counter is set to address 0h, so a current address

read of the RTC array starts at address 0h. When required,

as part of a random read, the master must supply the 1 Word

Address Bytes as shown in Figure 11.

In a random read operation, the slave byte in the “dummy

write” portion must match the slave byte in the “read”

section. For a random read of the Clock/Control Registers,

the slave byte must be “1101000x” in both places.

Write Operation

A Write operation requires a START condition, followed by a

valid Identification Byte, a valid Address Byte, a Data Byte,

and a STOP condition. After each of the three bytes, the

ISL12057 responds with an ACK. At this point, the I2C

interface enters a standby state.

Read Operation

A Read operation consists of a 3- byte instruction followed

by one or more Data Bytes (see Figure 11). The master

device initiates the operation by issuing the following

sequence: a START, the Identification byte with the R/W bit

set to “0”, an Address Byte, a second START, and a second

Identification byte with the R/W bit set to “1”. After each of

the three bytes, the ISL12057 responds with an ACK. Then,

the ISL12057 transmits Data Bytes, as long as the master

device responds with an ACK during the SCL cycle following

the eighth bit of each byte. The master device terminates the

read operation (issuing a STOP condition) following the last

bit of the last Data Byte (see Figure 11).

The Data Bytes are from the memory location indicated by

an internal pointer. This pointer’s initial value is determined

by the Address Byte in the Read operation instruction. It

increments by one during transmission of each Data Byte.

After reaching the memory location 13h, the pointer “rolls

over” to 00h, and the device continues to output data for

each ACK received.

FIGURE 9. SEQUENTIAL BYTE WRITE SEQUENCE

IDENTIFICATION

BYTE

FIRST DATA

BYTE

SIGNALS FROM

THE MASTER

SIGNALS FROM

THE ISL12057

WRITE

SIGNAL AT SDA

00 00

000

ADDRESS

BYTE

LAST DATA

BYTE

FIGURE 10. SLAVE ADDRESS, WORD ADDRESS, AND DATA

BYTES

SLAVE

ADDRESS BYTE

DATA BYTE

R/W

WORD ADDRESS

ISL12057

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